Отправлено Борода 28 мая 2002 г. 00:51

Синтез этого файла (ISE 4.1i,Synplify,Leonardo 2002a)выдает ошибки (хотелось получить схематик символы ap6 и Count_16 в одном проекте),
хотя пораздельно entity ap6 и Count_16 синтезируются без ошибок.

Что нет так.Подскажите пожалуйста.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ap6 is
port (signal ior,coz:in std_logic;
signal d_in: inout std_logic_vector(7 downto 0);
signal d_out: inout std_logic_vector(7 downto 0));
end ap6;

architecture behav1 of ap6 is
signal n_state: std_logic_vector(7 downto 0);
signal p_state: std_logic_vector(7 downto 0);

begin

d_out <= n_state when (coz = '0' and ior = '1')
else "ZZZZZZZZ";
d_in <= p_state when (coz = '0' and ior = '0')
else "ZZZZZZZZ";

n_state <= d_in;
p_state <= d_out;

end behav1;
------------------------------------------------
entity Count_16 is
Port ( CLK, Reset : in std_logic;
qout : out std_logic_vector(3 downto 0) );
end Count_16 ;

architecture bin of Count_16 is
signal Count : integer range 0 to 15;
Begin
ctr: process (CLK, Reset)
begin
if (Reset='1') then
Count <= 0;
elsif CLK'event and CLK = '1' then
if (Count >= 15) then
Count <= 0;
else
Count <= Count + 1;
end if;
end if;
end process;
qout <= conv_std_logic_vector (Count,4);
end bin;
-----------------------------------------------
Compiling vhdl file C:/My_Designs/AsicProjects/Ise4_1i/Test1/test1.vhd in Library work.
Architecture behav1 of Entity ap6 is up to date.
ERROR:HDLParsers:1203 - C:/My_Designs/AsicProjects/Ise4_1i/Test1/test1.vhd Line 29. std_logic: Undefined symbol.
ERROR:HDLParsers:1203 - C:/My_Designs/AsicProjects/Ise4_1i/Test1/test1.vhd Line 30. std_logic_vector: Undefined symbol.
Architecture bin of Entity count_16 is up to date.

• Ответ: — Serge   (28.05.2002 10:40, 162 байт)
  • Спасибо.Все получилось. — Борода   (28.05.2002 21:22, пустое)