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library IEEE;
use IEEE.std_logic_1164.all;
entity HDB3Decoder is
port (
CLK: in std_logic;
Pos: in std_logic;
Neg: in std_logic;
Data: out std_logic
);
end HDB3Decoder;
architecture HDB3Decoder_arch of HDB3Decoder is
signal ShReg: std_logic_vector(3 downto 0);
signal Buf: std_logic;
begin
Buf<=Pos or Neg;
process (CLK)
begin
if CLK'event and CLK='1' then
if (ShReg(2 downto 0)="001") then ShReg<="0000";
else
ShReg<=ShReg(2 downto 0) & Buf;
end if;
else null; end if;
end process;
Data<=ShReg(0);
end HDB3Decoder_arch;
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