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(«Телесистемы»: Конференция «Языки описания аппаратуры (VHDL и др.))

миниатюрный аудио-видеорекордер mAVR

Отправлено ТИМУР 07 августа 2002 г. 17:06
В ответ на: Ответ: Конечно он их не знал. отправлено Pashka 06 августа 2002 г. 15:42

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity look_up_table is
Port ( DW0 ,DW1 ,DW2 ,DW3 ,DW4 ,DW5 ,DW6 ,DW7 ,DW8 ,DW9 ,
DW10,DW11,DW12,DW13,DW14,DW15: in std_logic;
CLK,EPOCH,RESET : in std_logic;
CE_1,CE_2 : in std_logic;
Z1 : out std_logic;
Z2 : out std_logic;
Z3 : out std_logic;
Z4 : out std_logic;
Y1 : out std_logic;
Y2 : out std_logic;
Y3 : out std_logic;
Y4 : out std_logic;
FS0_OUT ,FS1_OUT ,FS2_OUT ,FS3_OUT ,FS4_OUT ,FS5_OUT ,FS6_OUT ,FS7_OUT ,FS8_OUT ,FS9_OUT ,
FS10_OUT,FS11_OUT,FS12_OUT,FS13_OUT,FS14_OUT,FS15_OUT,FS16_OUT,FS17_OUT,FS18_OUT,FS19_OUT,
FS20_OUT,FS21_OUT,FS22_OUT,FS23_OUT,FS24_OUT,FS25_OUT,FS26_OUT:out std_logic;
CPH0,CPH1,CPH2,CPH3,CPH4,CPH5,CPH6,CPH7:out std_logic);
end look_up_table;

architecture LOOK_UP of look_up_table is

component RG16
port (DW0,DW1,DW2,DW3,DW4,DW5,DW6,DW7,DW8,DW9,DW10,DW11,DW12,DW13,DW14,DW15,
CE,CLK: in std_logic;
FC0_OUT,FC1_OUT,FC2_OUT,FC3_OUT,FC4_OUT,FC5_OUT,FC6_OUT,FC7_OUT,FC8_OUT,FC9_OUT,
FC10_OUT,FC11_OUT,FC12_OUT,FC13_OUT,FC14_OUT,FC15_OUT: out std_logic);
end component;
component REGIN
port (FC0_IN ,FC1_IN ,FC2_IN ,FC3_IN ,FC4_IN ,FC5_IN ,FC6_IN ,FC7_IN ,FC8_IN ,FC9_IN ,
FC10_IN,FC11_IN,FC12_IN,FC13_IN,FC14_IN,FC15_IN,FC16_IN,FC17_IN,FC18_IN,FC19_IN,
FC20_IN,FC21_IN,FC22_IN,FC23_IN,FC24_IN,FC25_IN,
EPOCH,RESET,CLK:in std_logic;
D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,
D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,
D20,D21,D22,D23,D24,D25,D26:out std_logic);
end component;
component SUM
port (D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,
D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,
D20,D21,D22,D23,D24,D25,D26,RESET,CLK,EPOCH:in std_logic;
FS0 ,FS1 ,FS2 ,FS3 ,FS4 ,FS5 ,FS6 ,FS7 ,FS8 ,FS9 ,
FS10,FS11,FS12,FS13,FS14,FS15,FS16,FS17,FS18,FS19,
FS20,FS21,FS22,FS23,FS24,FS25,FS26,
CPH0,CPH1,CPH2,CPH3,CPH4,CPH5,CPH6,CPH7:out std_logic);
end component;
signal FC0 ,FC1 ,FC2 ,FC3 ,FC4 ,FC5 ,FC6 ,FC7 ,FC8 ,FC9 ,
FC10,FC11,FC12,FC13,FC14,FC15,FC16,FC17,FC18,FC19,
FC20,FC21,FC22,FC23,FC24,FC25,
D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,
D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,
D20,D21,D22,D23,D24,D25,D26,
FS0 ,FS1 ,FS2 ,FS3 ,FS4 ,FS5 ,FS6 ,FS7 ,FS8 ,FS9 ,
FS10,FS11,FS12,FS13,FS14,FS15,FS16,FS17,FS18,FS19,
FS20,FS21,FS22,FS23,FS24,FS25,FS26,
X1,X2,X3,X4,X5,znak:std_logic;

begin
R_LOW: RG16
port map (DW0 ,DW1 ,DW2 ,DW3 ,DW4 ,DW5 ,DW6 ,DW7 ,DW8 ,DW9 ,DW10,DW11,DW12,DW13,DW14,DW15,
CE_1,CLK,
FC0,FC1,FC2,FC3,FC4,FC5,FC6,FC7,FC8,FC9,FC10,FC11,FC12,FC13,FC14,FC15);
R_HIGH:RG16
port map (DW0 ,DW1 ,DW2 ,DW3 ,DW4 ,DW5 ,DW6 ,DW7 ,DW8 ,DW9 ,'0' ,'0' ,'0' ,'0' ,'0' ,'0' ,
CE_2,CLK,
FC16,FC17,FC18,FC19,FC20,FC21,FC22,FC23,FC24,FC25,'0' ,'0' ,'0' ,'0' ,'0' ,'0' );
REGACC: REGIN
port map (FC0 ,FC1 ,FC2 ,FC3 ,FC4 ,FC5 ,FC6 ,FC7 ,FC8 ,FC9 ,
FC10,FC11,FC12,FC13,FC14,FC15,FC16,FC17,FC18,FC19,
FC20,FC21,FC22,FC23,FC24,FC25,
EPOCH,RESET,CLK,
D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,
D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,
D20,D21,D22,D23,D24,D25,D26);
ACC:SUM
port map (D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,
D10,D11,D12,D13,D14,D15,D16,D17,D18,D19,
D20,D21,D22,D23,D24,D25,'0',
RESET,CLK,EPOCH,
FS0 ,FS1 ,FS2 ,FS3 ,FS4 ,FS5 ,FS6 ,FS7 ,FS8 ,FS9 ,
FS10,FS11,FS12,FS13,FS14,FS15,FS16,FS17,FS18,FS19,
FS20,FS21,FS22,FS23,FS24,FS25,FS26,
CPH0,CPH1,CPH2,CPH3,CPH4,CPH5,CPH6,CPH7);

FS0_OUT <= FS0;
FS1_OUT <= FS1;
FS2_OUT <= FS2;
FS3_OUT <= FS3;
FS4_OUT <= FS4;
FS5_OUT <= FS5;
FS6_OUT <= FS6;
FS7_OUT <= FS7;
FS8_OUT <= FS8;
FS9_OUT <= FS9;
FS10_OUT <= FS10;
FS11_OUT <= FS11;
FS12_OUT <= FS12;
FS13_OUT <= FS13;
FS14_OUT <= FS14;
FS15_OUT <= FS15;
FS16_OUT <= FS16;
FS17_OUT <= FS17;
FS18_OUT <= FS18;
FS19_OUT <= FS19;
FS20_OUT <= FS20;
FS21_OUT <= FS21;
FS22_OUT <= FS22;
FS23_OUT <= FS23;
FS24_OUT <= FS24;
FS25_OUT <= FS25;
FS26_OUT <= FS26;
X1 <= FS22;
X2 <= FS23;
X3 <= FS24;
X4 <= FS25;
X5 <= FS26;
znak<=(x1 or x2 or x3 or x4)and x5;
znsin:process (znak)
begin
y4<=znak;
end process znsin;
zncos:process (znak,x4)
begin
z4<=znak xor x4;
end process zncos;
hbit_sin:process(x1,x2,x3,x4)
begin
y1<=((not x1)and x2 and (not x3)and (not x4))or(x1 and (not x2)and (not x3))or((not x2)and (not x3)and x4)or((not x1)and(not x2)and x4)or((not x1)and x3 and x4)or(x2 and x3 and x4)or((not x1)and (not x2)and x3)or(x1 and x2 and x3);
end process hbit_sin;
hbit_cos:process(x1,x2,x3,x4)
begin
{Здесь моделсим выдает сообщение об ошибке: ERROR: look_up_table.vhd(136): Prefix of index must be an array.
# ERROR: look_up_table.vhd(136): Bad expression.
# ERROR: look_up_table.vhd(136): Bad expression.
# ERROR: look_up_table.vhd(136): Bad expression.
# ERROR: look_up_table.vhd(136): Bad expression.
# ERROR: look_up_table.vhd(136): Bad expression.
# ERROR: look_up_table.vhd(136): Bad expression.
# ERROR: look_up_table.vhd(136): Type error resolving infix expression.
# ERROR: look_up_table.vhd(154): VHDL Compiler exiting
# ERROR: C:/Modeltech_xe/win32xoem/vcom failed.}z1<=((not x2)and (not x3)and (not x4))or((not x1)and (not x2)and (not x4))or(x1 and (not x2)and (not x3))or((not x1)and x2(not x3)and x4)or((not x1)and (not x2)and x3)or(x1 and x2 and x3)or((not x1)and x3 and (not x4))or(x2 and x3 and (not x4));
end process hbit_cos;
mbit_sin:process(x1,x2,x3,x4)
begin
y2<=((not x1)and x2)or((not x3)and x4)or(x2 and x3 and (not x4))or(x1 and x3 and (not x4));
end process mbit_sin;
mbit_cos:process(x1,x2,x3,x4)
begin
z2<=((not x3)and (not x4))or((not x1)and x2)or(x2 and x3 and x4)or(x1 and x3 and x4);
end process mbit_cos;
lbit_sin:process(x1,x2,x3,x4)
begin
y3<=(x3 xor x4)or((not x2)and x4)or((not x2)and x3)or(x1 and x2 and (not x3))or(x1 and x2 and (not x4));
end process lbit_sin;
lbit_cos:process(x1,x2,x3,x4)
begin
z3<=((not x3)and (not x4))or((not x2)and (not x4))or(x1 and x2 and(not x3))or(x1 and x2 and x4)or(x3 and x4)or((not x2)and x3);
end process lbit_cos;
end LOOK_UP;

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