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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IObuf16 is
Port ( AD : inout std_logic_vector(15 downto 0);
OE,WE : in STD_LOGIC;
DataRAM : inout std_logic_vector(15 downto 0);
DataIN : inout std_logic_vector(15 downto 0);
DATAOUT : inout std_logic_vector(15 downto 0));
end IObuf16;
architecture Behavioral of IObuf16 is
component ibuf is
port(
O : out std_ulogic;
I : in std_ulogic);
end component;
component obuft is
port(
O : out std_ulogic;
I : in std_ulogic;
T : in std_ulogic);
end component;
begin
AD_WE_Data: for S in 0 to 15 generate
ID41: ibuf port map(O => DataIN(S),I => AD(S));
end generate;
AD_RD_Data: for S in 0 to 15 generate
ID42: OBUFT port map(O => AD(S),I => DATAOUT(S),T => OE);
end generate;
Ram_WE_Data: for S in 0 to 15 generate
ID43: ibuf port map(O => DATAOUT(S),I => DataRAM(S));
end generate;
Ram_RD_Data: for S in 0 to 15 generate
ID44: OBUFT port map(O => DataRAM(S),I => DataIN(S),T => WE);
end generate;
end Behavioral;
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