Отправлено 3.14 19 сентября 2002 г. 19:59

При суммировании всех регистров tRegx в регистр ttReg1, сложение выполняется
без учета переполнения. Что можно сделать, дабы это устранить, кроме увеличения разрядности
входных регистров tRegx?
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity math_rls_filter is
Port ( inDATA : in std_logic_vector(7 downto 0);
outDATA : out std_logic_vector(7 downto 0);
strobPix : in std_logic
);
end math_rls_filter;

architecture Behavioral of math_rls_filter is
signal tReg1 : std_logic_vector(7 downto 0);
signal tReg2 : std_logic_vector(7 downto 0);
signal tReg3 : std_logic_vector(7 downto 0);
signal tReg4 : std_logic_vector(7 downto 0);
signal tReg5 : std_logic_vector(7 downto 0);
signal tReg6 : std_logic_vector(7 downto 0);
signal tReg7 : std_logic_vector(7 downto 0);
signal tReg8 : std_logic_vector(7 downto 0);
signal tReg9 : std_logic_vector(7 downto 0);
signal tReg10 : std_logic_vector(7 downto 0);
signal ttReg1 : std_logic_vector(15 downto 0);

constant ttReg2 : std_logic_vector(15 downto 0) := "0001100110011001"; -- 1/10
signal ttReg3 : std_logic_vector(31 downto 0);

begin
-- ------------------- Start --------------------

ttReg1(15 downto 0) <= (unsigned(tReg1)+unsigned(tReg2)+unsigned(tReg3)+unsigned(tReg4)+unsigned(tReg5)+unsigned(tReg6)+unsigned(tReg7)+unsigned(tReg8)+unsigned(tReg9)+unsigned(tReg10));
ttReg3 <= unsigned(ttReg1)*unsigned(ttReg2);
outDATA <= ttReg3(23 downto 16);

process(strobPix)
begin
if strobPix'event and strobPix='1' then
tReg10 <= tReg9;
tReg9 <= tReg8;
tReg8 <= tReg7;
tReg7 <= tReg6;
tReg6 <= tReg5;
tReg5 <= tReg4;
tReg4 <= tReg3;
tReg3 <= tReg2;
tReg2 <= tReg1;
tReg1(7 downto 0) <= inDATA(7 downto 0);
end if;
end process;

end Behavioral;