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For multi-master systems, be aware that the BB bit does not reflect the bus status until the I2C peripheral is out of
reset (IRS set to “1”) and the first START or STOP condition is detected. Before initiating the first data transfer with
the I2C peripheral, follow this sequence:
1. After taking the I2C peripheral out of reset (IRS bit set to “1”), wait a certain period to detect the actual
bus status before starting the first data transfer. [The period should be set longer than the total time it
takes for the longest data transfer in the application.] Waiting this amount of time after the I2C comes
out of reset should ensure at least one START or STOP condition occurred on the I2C bus and captured
by the BB bit. After this period, the BB bit will correctly reflect the state of the I2C bus.
2. Poll the BB bit and verify that BB = 0 (bus not busy) before proceeding to next step.
3. Begin data transfers.
4. Do not reset the I2C peripheral between transfers so that the BB bit reflects the actual bus status. If the
I2C peripheral must be reset between transfers, repeat steps 1 through 3 every time the I2C peripheral
is taken out of reset (IRS bit set to “1”).
(Internal reference number: 1474)
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