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CONSTANT DEVICES=8;subdesign test1
(
clk, reset: input;
ack[DEVICES-1..0]:output;
req[DEVICES-1..0]:input;
)
variable
areg[DEVICES-1..0]:DFFE;
tmp[DEVICES-1..0]:NODE;
begin
areg[].clk = clk; areg[].clrn = !reset;
tmp[] = (req[DEVICES-2..0] # tmp[DEVICES-2..0], GND);
if (areg[]==0) then
areg[]=VCC;
areg[].ena = req[] & !tmp[DEVICES-1..0];
else
areg[]=0;
areg[].ena=!req[];
end if;
ack[]=areg[];
end;
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