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reg start_or_stop;
wire sda_n;
assign sda_n = sda;
always@(negedge sda, negedge sda_n)
begin
if(scl==1 & sda == 0)start_or_stop = 1;
if(scl==1 & sda == 1)start_or_stop = 0;
end
результат тот же что и при always@(sda).
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