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Код:
module test(
input clk,
input signed [3:0] in,
output signed [7:0] out);
parameter signed [3:0] coeff0 = 10'b1010; // -6 or 10
reg signed [3:0] temp;
assign out = temp * coeff0;
always @(posedge clk) temp <= in;
endmodule
работает верно. В симуляторе Quartus-а при in=-3 out=18, при in=5 out=-30.
Код:
module test(
input clk,
input signed [3:0] in,
output signed [7:0] out);
parameter signed [3:0] coeff0 = 10'b1010; // -6 or 10
reg signed [3:0] temp [1:0];
assign out = temp[0] * coeff0;
always @(posedge clk) temp[0] <= in;
endmodule
В симуляторе Quartus-а при in=-3 out=-126, при in=5 out=50. Т.е. умножитель стал беззнаковым.
Этой чей глюк. Помогите разобраться.
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