module case_test (in, out1, out2);
input [1:0] in;
output reg [1:0] out1, out2;

always @*
case (in)
0 : begin out1=3; out2=2; end
1 : begin out1=2; out2=3; end
2 : begin out1=1; out2=0; end
3 : begin out1=0; out2=1; end
endcase

endmodule