.macro	WriteReg
	ldi	xl,LOW(@0)
	ldi	xh,BYTE2(@0)
	ldi	yl,BYTE3(@0)
	ldi	yh,BYTE4(@0)
	rcall	TranseiverWriteReg32
.endmacro

;**********************************************************
;**********************************************************
;**********************************************************
_TransceiverInit:
	SLE_OFF
	DATA_HIZ
	SCLK_OFF
;
	WriteReg	0x4+(DEMOD_SCHEME<<4)+(DOT_PRODUCT<<7)+(RX_INVERT<<8)+(DISCRIMINATOR_BW<<10)+(POST_DEMOD_BW<<20)+(IF_BW<<30)
	WriteReg	0x3+(BBOS_CLK_DIVIDER<<4)+(DEM_CLK_DIVIDER<<6)+(CDR_CLK_DIVIDER<<10)+(SEQ_CLK_DIVIDER<<18)+(AGC_CLK_DIVIDER<<26)
	WriteReg	0x2+(MODULATION_SCHEME<<4)+(PA_ENABLE<<7)+(PA_RAMP<<8)+(PA_BIAS<<11)+(PA_LEVEL<<13)+(TX_FREQUENCY_DEVIATION<<19)+(TX_DATAINVERT<<28)+(RCOS_ALPHA<<30)
	WriteReg	0x1+(R_COUNTER<<4)+(CLOCKOUT_DIVIDE<<7)+(XTAL_DOUBLER<<11)+(XOSC_ENABLE<<12)+(XTAL_BIAS<<13)+(CP_CURRENT<<15)+(VCO_ENABLE<<17)+(RF_DIVIDE_BY_2<<18)+(VCO_BIAS<<19)+(VCO_ADJAST<<23)+(VCO_INDUCTOR<<25)
	
;
	ret

EOF

.....

Файл ADF7021.INC

#ifndef	_ADF7021INC_

#define	_ADF7021INC_

#define	DivAndRound(A,B)		((A)/(B)+2*((A)%(B))/(B))


;**********************************************************
;
;	ADF7021 INIT CONSTANTS
;
;**********************************************************
#define	XTAL			19680000

; XTAL/2 = [2MHz;15MHz]
#define	DEMOD_CLK			9840000
#define	TX_DEVIATION		7500

; bitrate*0.75
#define	POST_DEMODULATION_BW	15000

; 0-12.5KHz 1-18.75KHz 2-25KHz
#define	IF_BW			2

;
;	START ISM
;
#define	INTEGER_N			44
#define	FRACTION_N		300
#define	FRACTION_STEP		84

;
;
;
#define	AGC_HIGH_THRESHOLD		70
#define	AGC_LOW_THRESHOLD		30


;
;	REG0 N-REGISTER
;
#define	TX_DISABLE		1
#define	UART_MODE			1
#define	MUXOUT			12

;
;	REG1 VCO/OSCILLATOR REGISTER
;
#define	R_COUNTER			1
#define	CLOCKOUT_DIVIDE		0
#define	XTAL_DOUBLER		0

; External oscillator with 0.8Vp-p
#define	XOSC_ENABLE		1

; 30 mkA
#define	XTAL_BIAS			2

; 1.5 mA
#define	CP_CURRENT		2

#define	VCO_ENABLE		1
#define	RF_DIVIDE_BY_2		1

; 2.5 mA
#define	VCO_BIAS			10

#define	VCO_ADJAST		0
#define	VCO_INDUCTOR		0

;
;	SPARE CONSTS
;
#define	_PFD_			(((1+XTAL_DOUBLER)*(XTAL/R_COUNTER))>>RF_DIVIDE_BY_2)

;
;	REG2 TRANSMIT MODULATION REGISTER
;
; OVERSAMPLED 2FSK
#define	MODULATION_SCHEME		4

; PA IS ENABLED
#define	PA_ENABLE			1

; NO RAMPING
#define	PA_RAMP			0

; 11mkA
#define	PA_BIAS			3

; 13dBm			
#define	PA_LEVEL			63

#define	TX_FREQUENCY_DEVIATION	(DivAndRound((TX_DEVIATION<<16),_PFD_))

#define	TX_DATAINVERT		0
#define	RCOS_ALPHA		0	

;
;	REG3 CLOCK REGISTER
;
; ~1.5MHz (1MHz;2MHz)
#define	BBOS_CLK_DIVIDER		(DivAndRound(XTAL,4*1500000)-1)

; 7MHz [2MHz;15MHz]
#define	DEM_CLK_DIVIDER		(DivAndRound(XTAL,DEMOD_CLK))


; DEM_CLK/100 
#define	CDR_CLK_DIVIDER		100		

; -> 100 KHz	
#define	SEQ_CLK_DIVIDER		(DivAndRound(XTAL,100000))

; SEQ_CLK/x -> 10 KHz
#define	AGC_CLK_DIVIDER		10

;
;	SPARE CONSTS
;
#define	_KK_			_K_
#define	_K_			(DivAndRound(100000,TX_DEVIATION))

#if	_KK_ & 1

 #define	DOT_PRODUCT		1
 #if	((_KK_+1)/2) & 1
  #define	RX_INVERT			2
 #else
  #define	RX_INVERT			0
 #endif


#else

 #define	DOT_PRODUCT		0
 #if	((_KK_)/2) & 1
  #define	RX_INVERT			2
 #else
  #define	RX_INVERT			0
 #endif

  
#endif

;
;	REG4 DEMODULATOR SETUP REGISTER
;
; 2FSKCORRELATOR DEMODULATOR
;
#define	DEMOD_SCHEME		1
#define	DISCRIMINATOR_BW		(DivAndRound(XTAL,(4*TX_DEVIATION*DEM_CLK_DIVIDER)))
#define	POST_DEMOD_BW		(DivAndRound(6434*POST_DEMODULATION_BW,DEMOD_CLK))



				


#endif