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Выдержки из даташита:
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Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation.
Once power is applied to VDD and VDDQ (simultaneously)
and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to applying any command other than a COMMAND
INHIBIT or a NOP. Starting at some point
during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100µs delay has been satisfied, with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
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Контроллер SDRAM сам запишет требуемое значение в MODE REGISTER?
А откуда он его знает? Или назначение битов Mode Register унифицированы для всех SDRAM?
E-mail: 
info@telesys.ru
