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Синтез, приведенного ниже блочка, проходит на ура, - при имплиментации(на этапе translate) выдаётся следующее:
Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'ce_a_bufgp' has non-clock connections. These
problematic connections include: pin d on block avtom_0 with type FDC, pin i0
on block ker46271 with type LUT2, pin i1 on block _n0167_sw1 with type LUT3
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Сразу хоче сказать - сигнал "CE" - не является глобальным клоком. Несмотря на данный глюк - на построенных диаграммах данный блочек работает так как надо - но на реальном железе (XC2s100) "работает" очень криво.
Как выяснилось, вся фишка в том, что сигнал СЕ в первом процессе используется как клок, а во втором пропускается через логику - на цифровом втомате ловится задний фронт СЕ - НО Я НЕ ВИЖУ причины по которой ISE не может развести какието цепи!!!
ОБЬЯСНИТЕ дураку что это такое и как с этим бороться!!!
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY control_ram_b IS
PORT (
reset : in std_logic;
clk : in std_logic;
correkt_ab : in std_logic_vector (1 downto 0);
numberTS_C_out : in integer range 31 downto 0;
numberFR_C_out : IN integer range 15 downto 0;
numberTS_A : in integer range 31 downto 0;
bufA : in std_logic_vector (7 downto 0);
ce_a : in std_logic;
start_a : in boolean;
buf_tso_A1 : in std_logic_vector (3 downto 0);
buf_tso_A2 : in std_logic_vector (3 downto 0);
data_out_a : in std_logic_vector (7 downto 0);
we_a : out std_logic;
addr_a : out std_logic_vector (8 downto 0);
wr_data_a : out std_logic_vector (7 downto 0);
read_data_a : out std_logic_vector (7 downto 0)
);
END control_ram_b;
ARCHITECTURE control_ram_body OF control_ram_b IS
-------------------------------
signal address_wr_a : std_logic_vector (8 downto 0);
signal ts_a_tp : std_logic_vector (7 downto 0);
signal byte : std_logic_vector (3 downto 0);
signal work_fl : std_logic;
-- signal work_end : std_logic;
signal we_fl : std_logic;
signal work_ts : std_logic_vector(7 downto 0);
-- signal work : std_logic_vector(7 downto 0);
--------------------------------
BEGIN
process (reset,ce_a,start_a)
variable i : integer range 4 downto 0;
variable v : integer range 1 downto 0;
variable f,ff : std_logic;
begin
if (reset = '0' or start_a = false) then
i := 0;
f := '0';
ff := '0';
ts_a_tp <= conv_std_logic_vector (0,8);
work_ts <= conv_std_logic_vector (0,8);
-- work <= conv_std_logic_vector (0,8);
byte <= conv_std_logic_vector (0,4);
v := 0;
elsif (ce_a'event and ce_a = '0') then
if start_a = false then
i := 0;
ts_a_tp <= conv_std_logic_vector (0,8);
work_ts <= conv_std_logic_vector (0,8);
-- work <= conv_std_logic_vector (0,8);
byte <= conv_std_logic_vector (0,4);
v := 0;
f := '0';
end if;
we_fl <= '0';
if i = 4 then
if numberTS_A /= 4 and numberTS_A /= 21 then -- 6 =0
case v is
when 0 =>
if ff = '0' then
byte <= buf_tso_A2;
else
byte <= buf_tso_A1;
end if;
if f = '1' then
we_fl <= '1';
end if;
when 1 =>
if ff = '0' then
ts_a_tp(3 downto 0) <= buf_tso_A1;
ts_a_tp(7 downto 4) <= byte;
else
ts_a_tp(3 downto 0) <= buf_tso_A2;
ts_a_tp(7 downto 4) <= byte;
end if;
f := '1';
when others =>
end case;
if numberTS_A = 9 then--and safe_A = '1' then
work_ts <= bufA;--"00001111";--
end if;-- ts_a_tp(7 downto 4) <= buf_tso_A1;
v := v + 1;
else
if numberTS_A = 21 then
ts_a_tp(3 downto 0) <= buf_tso_A2;
end if;
ff := not ff;
we_fl <= '0';
end if;
end if;
if i /= 4 then
i := i + 1;
end if;
end if;
end process;
------------------------------------------------------------------
process (clk,reset)
variable count : integer range 5 downto 0;
variable avtom : integer range 1 downto 0;
begin
if (reset = '0') then
addr_a <= conv_std_logic_vector(0,9);
wr_data_a <= conv_std_logic_vector(0,8);
address_wr_a <= conv_std_logic_vector(2,9);
we_a <= '0';
count := 0;
avtom := 0;
elsif (clk'event and clk = '1') then
if start_a = false then
addr_a <= conv_std_logic_vector(0,9);
wr_data_a <= conv_std_logic_vector(0,8);
address_wr_a <= conv_std_logic_vector(2,9);
we_a <= '0';
count := 0;
avtom := 0;
end if;
case avtom is
when 0 =>
if ce_a = '1' then
avtom := 1;
end if;
when 1 =>
if ce_a = '0' then
avtom := 0;
count := 0;
work_fl <= '1';
end if;
when others =>
end case;
-- work_end <= '0';
if work_fl = '1' then
case count is
when 0 =>
count := count + 1;
if we_fl = '1' then
addr_a <= address_wr_a;
if numberTS_A = 5 or numberTS_A = 19 then -- 7 = 0
address_wr_a <= address_wr_a + 3;
else
address_wr_a <= address_wr_a + 2;
end if;
end if;
when 1 =>
count := count + 1;
if we_fl = '1' then
wr_data_a <= ts_a_tp;
if numberTS_A = 7 then
wr_data_a <= work_ts;
end if;
end if;
when 2 =>
count := count + 1;
if we_fl = '1' then
we_a <= '1';
end if;
when 3 =>
count := count + 1;
we_a <= '0';
when 4 =>
count := count + 1;
if correkt_ab = "01" then
addr_a <= conv_std_logic_vector (numberTS_C_out + (numberFR_C_out-1)*32,9);
end if;
when 5 =>
count := 0;
read_data_a <= data_out_a;
work_fl <= '0';
when others =>
read_data_a <= conv_std_logic_vector(0,8);
end case;
else
count := 0;
end if;
end if;
end process;
END control_ram_body;
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