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я привел лишь предположение, лежащее на поверхности, в справедливости которого я сомневаюсь. надеялся получить к нему комментарии, другие идеи.
тип ИКМ-порта соответствует интерфейсу 1024кБит/с (коды AMI/OMC) аппаратуры ИКМ15/30 "КЕДР", ИКМ15 "ИВА"..
имел ввиду, что примененный механизм синхронизации использовался в предидущих моделях с интегральными приемопередатчиками и работал.
поскольку не считаю возможным заставлять читать ~300 строк кода всего
приемопередатчика интересует концептуальная идея - где находится ошибка .
итак, еще раз:
виноват ли приемник?
приемник работает, т.к. находит синхронизацию приемного сигнала, при условии, что его источник не находится в режиме синхр от приема.
виновата ли схема выделения тактовой частоты? (наиболее вероятно, поэтому хотелось бы слышать мнение люде пользовавшихся этим кодом).
использованный мною dpll проверен как мною так и автором статьи Чип-Ньюз, рекомендован одним из членов конференции.
при моделировании различных ситуаций по совпадениям перепадов проблем не возникает.
действительно ли данный dpll имеет ограничение работоспособности в
зависимости от момента прихода входного сигнала?
просьба если есть - еще идеи где есть ошибка
(налицо неоднозначность с ее локализацией)
ниже привожу код dpll
----------------------------------------------------------------------------------------------
-- VHDL file generated by X-HDL - Revision 3.1.20
-- Sat Dec 21 17:47:22 2002
--
-- Input file : E:\personnel\serg\found.pr\tic\source/pll/dpll_with_rwf/eng/phasecomparatore.v
-- Design name : phasecomparator
-- Author : jm
-- Company : sts
--
-- Description : phase comparator
----------------------------------------------------------------------------------------------
library work;
use work.exemplar_1164.all;
library ieee;
use ieee.std_logic_1164.all;
ENTITY phasecomparator IS
PORT (
InputSignal : IN std_logic; -- input siganals
OutputSignal : IN std_logic; -- input siganals
MainClock : IN std_logic; -- reference clock
Lead : OUT std_logic; -- control signals
Lag : OUT std_logic); -- control signals
END phasecomparator;
ARCHITECTURE trans OF phasecomparator IS
SIGNAL InputSignalEdgeDet : std_logic_vector(1 DOWNTO 0); -- input signal rising edge detector
-- signal can be delayed for two MainClock(?) periods
-- to reduce the const phase error of the comparator the output freq
-- signal rising edge. in consequence the output freq level is checked
-- this siganal is checked on MainClock rising edge and detects the input
SIGNAL InputSignalEdge : std_logic;
-- on rising edge of input clock
-- lead siganl is generated when level 1 is detected on output freq signal
SIGNAL Lea : std_logic;
SIGNAL La : std_logic;
BEGIN
Lead <= Lea;
Lag <= La;
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '1');
InputSignalEdgeDet <= InputSignalEdgeDet(0) & InputSignal;
END PROCESS;
InputSignalEdge <= bool2elb(InputSignalEdgeDet = "01") ;
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '0');
La <= bool2elb((InputSignalEdge = '1') AND (OutputSignal = '0'));
Lea<= bool2elb((InputSignalEdge = '1') AND (OutputSignal = '1'));
END PROCESS;
END trans;
----------------------------------------------------------------------------------------------
-- VHDL file generated by X-HDL - Revision 3.1.20
-- Sat Dec 21 17:47:17 2002
--
-- Input file : E:\personnel\serg\found.pr\tic\source/pll/dpll_with_rwf/eng/freqdividere.v
-- Design name : freqdivider
-- Author : jm
-- Company : sts
--
-- Description : freq divider and phase control logic
----------------------------------------------------------------------------------------------
library work;
use work.exemplar_1164.all;
library ieee;
use ieee.std_logic_1164.all;
ENTITY freqdivider IS
PORT (
MainClock : IN std_logic; -- ref clock
Positive : IN std_logic; -- local signals Positive, Negative synchronous to MainClock
Negative : IN std_logic; -- local signals Positive, Negative synchronous to MainClock
FrequencyOut : OUT std_logic; -- output clock
Frequency2Out : OUT std_logic); -- output 2xclock
END freqdivider;
ARCHITECTURE trans OF freqdivider IS
-- required counter modulo
CONSTANT DividerLength : integer := 4;
-- fcentre= 1Mhz and fref=16384khz
-- resulting ratio is product of these 2*8=16
-- logic contains variable count divider and divider by 2 (for 50% duty cycle)
CONSTANT DividerMaxValue : integer := 8;
SIGNAL Div : std_logic_vector(DividerLength - 1 DOWNTO 0);
SIGNAL Freq : std_logic_vector(1 downto 0);
BEGIN
FrequencyOut <= Freq(1);
Frequency2Out <= Freq(0);
-- here is the division scenario when randomwalkfilter signals are used
-- lag signal is responded the counter is incremented by 2 (not 1)
-- lead signal is responded the counter is not changed
-- in case of absence of control signals (when there's no phase error)
-- the counter is incremented by 1
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '1');
IF (Div >= int2evec((DividerMaxValue - 1), 4)) THEN Div <= "0000";
ELSE
IF (Negative = '1') THEN Div <= Div + "0010";
ELSE
IF (Positive = '1') THEN Div <= Div;
ELSE
Div <= Div + "0001";
END IF;
END IF;
END IF;
END PROCESS;
PROCESS -- divider by 2
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '0');
IF (Div(1 downto 0) = "00") THEN
Freq <= Freq - "01";
END IF;
END PROCESS;
END trans;
----------------------------------------------------------------------------------------------
-- VHDL file generated by X-HDL - Revision 3.1.20
-- Sat Dec 21 17:47:29 2002
--
-- Input file : E:\personnel\serg\found.pr\tic\source/pll/dpll_with_rwf/eng/randomwalkfiltere.v
-- Design name : randomwalkfilter
-- Author : jm
-- Company : sts
--
-- Description : zero reset randomwalkfilter
----------------------------------------------------------------------------------------------
library work;
use work.exemplar_1164.all;
library ieee;
use ieee.std_logic_1164.all;
ENTITY randomwalkfilter IS
generic ( FilterResetValue : integer := 4 ) ;
PORT (
MainClock : IN std_logic; -- ref clock
Lead : IN std_logic; -- PC siganl
Lag : IN std_logic; -- PC siganl
Positive : OUT std_logic; -- pos shift output
Negative : OUT std_logic); -- neg shift output
END randomwalkfilter;
ARCHITECTURE trans OF randomwalkfilter IS
-- constants/generics
CONSTANT FilterLength : integer := 8;
CONSTANT FilterMaxValue : integer := FilterResetValue;
CONSTANT FilterMinValue : integer := 256 - FilterResetValue;
-- reversible counter
SIGNAL FilterCounter : std_logic_vector(FilterLength - 1 DOWNTO 0);
-- lag and lead are generated when minimal or maximal counter output
SIGNAL Posi : std_logic;
SIGNAL Nega : std_logic;
BEGIN
Positive <= Posi;
Negative <= Nega;
-- input sync to MainClock pulses counter
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '1');
IF ((FilterCounter = int2evec(FilterMaxValue, 8)) OR
(FilterCounter = int2evec(FilterMinValue, 8))) THEN FilterCounter <= "00000000";
ELSE
IF (Lead = '1') THEN FilterCounter <= FilterCounter + "00000001";
END IF;
IF (Lag = '1') THEN FilterCounter <= FilterCounter - "00000001";
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '0');
Posi <= bool2elb(FilterCounter = int2evec(FilterMaxValue, 8));
Nega <= bool2elb(FilterCounter = int2evec(FilterMinValue, 8));
END PROCESS;
END trans;
----------------------------------------------------------------------------------------------
-- VHDL file generated by X-HDL - Revision 3.1.20
-- Sat Dec 21 17:47:37 2002
--
-- Input file : E:\personnel\serg\found.pr\tic\source/pll/dpll_with_rwf/eng/variableresetrandomwalkfiltere.v
-- Design name : variableresetrandomwalkfilter
-- Author : jm
-- Company : sts
--
-- Description : variable reset random walk filter
----------------------------------------------------------------------------------------------
library work;
use work.exemplar_1164.all;
library ieee;
use ieee.std_logic_1164.all;
ENTITY variableresetrandomwalkfilter IS
PORT (
MainClock : IN std_logic; -- ref clock
Lead : IN std_logic; -- PC signal
Lag : IN std_logic; -- PC signal
Positive : OUT std_logic; -- pos shift output
Negative : OUT std_logic); -- neg shift output
END variableresetrandomwalkfilter;
ARCHITECTURE trans OF variableresetrandomwalkfilter IS
COMPONENT randomwalkfilter
generic ( FilterResetValue : integer);
PORT (
MainClock : IN std_logic;
Lead : IN std_logic;
Lag : IN std_logic;
Positive : OUT std_logic;
Negative : OUT std_logic);
END COMPONENT;
CONSTANT N_FilterLength : integer := 8;
CONSTANT N_FilterResetValue : integer := 8;
CONSTANT N_FilterMaxValue : integer := N_FilterResetValue;
-- 256=2^8(counter length). is used cause of unsigned arith
CONSTANT N_FilterMinValue : integer := 256 - N_FilterResetValue;
-- reset logic counter length is taken short
CONSTANT ResetterCounterLength : integer := 4;
CONSTANT ResetterCounterMaxValue : integer := 3;
-- 16=2^4(counter length). is used cause of unsigned arith
CONSTANT ResetterCounterMinValue : integer := 16 - 3;
-- N rwf counter
SIGNAL N_FilterCounter : std_logic_vector(N_FilterLength - 1 DOWNTO 0);
-- M rwf counter instantiation
SIGNAL Up : std_logic;
SIGNAL Down : std_logic;
-- reset logic counter changes its value in response to M counter signals
SIGNAL ResetterCounter : std_logic_vector(ResetterCounterLength - 1 DOWNTO 0);
-- reset counter to N counter reset value decoder table
SIGNAL ResetterValue : std_logic_vector(N_FilterLength - 1 DOWNTO 0);
-- lag and lead are generated when minimal or maximal N counter output
SIGNAL Posit : std_logic;
SIGNAL Negat : std_logic;
BEGIN
Positive <= Posit;
Negative <= Negat;
inst_M_Filter : randomwalkfilter
GENERIC MAP (FilterResetValue => 32)
PORT MAP ( MainClock => MainClock, Lead => Lead, Lag => Lag, Positive => Up, Negative => Down);
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '1');
IF (Up = '1') THEN
IF ((ResetterCounter < int2evec(ResetterCounterMaxValue, 4)) OR
(ResetterCounter >= int2evec(ResetterCounterMinValue, 4)))
THEN ResetterCounter <= ResetterCounter + "0001";
END IF;
ELSE
IF (Down = '1') THEN
IF ((ResetterCounter<=int2evec(ResetterCounterMaxValue, 4)) OR
(ResetterCounter > int2evec(ResetterCounterMinValue, 4)))
THEN ResetterCounter <= ResetterCounter - "0001";
END IF;
END IF;
END IF;
IF ((ResetterCounter > int2evec(ResetterCounterMaxValue, 4)) AND
(ResetterCounter < int2evec(ResetterCounterMinValue, 4)))
THEN ResetterCounter <= "0000";
END IF;
END PROCESS;
PROCESS (ResetterCounter)
BEGIN
CASE ResetterCounter IS
-- WHEN int2evec(16 - 3, 4) => ResetterValue <= int2evec(256 - 7, 8);
-- WHEN int2evec(16 - 2, 4) => ResetterValue <= int2evec(256 - 6, 8);
-- WHEN int2evec(16 - 1, 4) => ResetterValue <= int2evec(256 - 4, 8);
when "1101" => ResetterValue <= int2evec(256 - 4, 8);
WHEN "1110" => ResetterValue <= int2evec(256 - 4, 8);
WHEN "1111" => ResetterValue <= int2evec(256 - 4, 8);
WHEN "0000" => ResetterValue <= "00000000";
WHEN "0001" => ResetterValue <= "00000100";
WHEN "0010" => ResetterValue <= "00000110";
WHEN "0011" => ResetterValue <= "00000111";
WHEN OTHERS => ResetterValue <= "00000000";
END CASE;
END PROCESS;
-- N rwf counter, its variable reset value is stored in ResetterValue ff
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '1');
IF ((N_FilterCounter = int2evec(N_FilterMaxValue, 8)) OR
(N_FilterCounter = int2evec(N_FilterMinValue, 8)))
THEN N_FilterCounter <= ResetterValue;
ELSE
IF (Lead = '1') THEN N_FilterCounter <= N_FilterCounter + "00000001";
END IF;
IF (Lag = '1') THEN N_FilterCounter <= N_FilterCounter - "00000001";
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (MainClock'EVENT AND MainClock = '0');
Posit <= bool2elb(N_FilterCounter = int2evec(N_FilterMaxValue, 8));
Negat <= bool2elb(N_FilterCounter = int2evec(N_FilterMinValue, 8));
END PROCESS;
END trans;
----------------------------------------------------------------------------------------------
-- VHDL file generated by X-HDL - Revision 3.1.20
-- Sat Dec 21 17:47:43 2002
--
-- Input file : E:\personnel\serg\found.pr\tic\source/pll/dpll_with_rwf/eng/dplle.v
-- Design name : dpll
-- Author : jm
-- Company : sts
--
-- Description : top module
----------------------------------------------------------------------------------------------
library work;
use work.exemplar_1164.all;
library ieee;
use ieee.std_logic_1164.all;
ENTITY dpll IS
PORT (
SignalIn : IN std_logic; -- input freq
SignalOut : OUT std_logic; -- output freq
Signal2Out : OUT std_logic; -- output 2xfreq
MainClock : IN std_logic; -- refenrence freq
Positive : OUT std_logic; -- local
Negative : OUT std_logic; -- local
Lead : OUT std_logic; -- local
Lag : OUT std_logic); -- local
END dpll;
ARCHITECTURE trans OF dpll IS
COMPONENT freqdivider
PORT (
MainClock : IN std_logic;
Positive : IN std_logic;
Negative : IN std_logic;
FrequencyOut : OUT std_logic;
Frequency2Out : OUT std_logic);
END COMPONENT;
COMPONENT phasecomparator
PORT (
InputSignal : IN std_logic;
OutputSignal : IN std_logic;
MainClock : IN std_logic;
Lead : OUT std_logic;
Lag : OUT std_logic);
END COMPONENT;
COMPONENT variableresetrandomwalkfilter
PORT (
MainClock : IN std_logic;
Lead : IN std_logic;
Lag : IN std_logic;
Positive : OUT std_logic;
Negative : OUT std_logic);
END COMPONENT;
SIGNAL Sig : std_logic;
SIGNAL Sig2 : std_logic;
SIGNAL Ps : std_logic;
SIGNAL Ng : std_logic;
SIGNAL Ld : std_logic;
SIGNAL Lg : std_logic;
BEGIN
SignalOut <= Sig;
Signal2Out <= Sig2;
Positive <= Ps;
Negative <= Ng;
Lead <= Ld;
Lag <= Lg;
--phase comparator instantiation
inst_ph_cmp : phasecomparator
PORT MAP ( MainClock => MainClock, InputSignal => SignalIn, OutputSignal => Sig, Lead => Ld, Lag => Lg);
-- Zero-Reset Random Walk Filter instantiation as inst_rwf assumes Variable-Reset Random Walk Filter instantiation is commented
--inst_rwf : randomwalkfilter
--PORT MAP (MainClock => MainClock, Lead => Ld, Lag => Lg, Positive => Ps, Negative => Ng);
--Variable-Reset Random Walk Filter instantiation Zero-Reset Random Walk Filter instantiation is commented
inst_rwf : variableresetrandomwalkfilter
PORT MAP ( MainClock => MainClock, Lead => Ld, Lag => Lg, Positive => Ps, Negative => Ng);
--ref frequency divider and filter controls instantiation
inst_freqdiv : freqdivider
PORT MAP ( MainClock => MainClock, FrequencyOut => Sig, Frequency2Out => Sig2, Positive => Ps, Negative => Ng);
END trans;
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